The present invention relates to a method of wiring semiconductor integrated circuits, and more particularly to a wiring technique for semiconductor integrated circuits of multilayered structures considering the signal transmission delay time effectively applicable to a wiring method for semiconductor integrated circuits which possibly reduces variations in signal transmission delay time in crossed wires between layers.
Conventional wiring methods for semiconductor integrated circuits considering the signal transmission delay time concern semiconductor integrated circuits, as disclosed in JP-A-64-42146, which have a buffer gate inserted between gates to shorten the wiring length between gates for an improved processing speed while preventing the rounding of the signal waveform.
The conventional wiring methods, which are intended to consider an increased signal transmission delay time due to a lengthened wiring length, fail to consider the delay time caused between the object wire, such as a clock signal wire and other wires crossing it. Such conventional wiring methods also pose problem such as variations caused in delay time according to the number of crossed wires even for a small delay time.
The conventional wiring methods, therefore, cannot be applied successfully to semiconductor integrated circuits using clock signal wires requiring an appropriate timing.